The present invention relates to a semiconductor memory device, and more particular to a timing signal generator for column selection in a dynamic type semiconductor memory device.
A dynamic memory device is structured such that a plurality of memory cells are arranged in a matrix form of rows with word lines and columns with a plurality of pairs of digit lines and a plurality of sense amplifiers are provided for the plurality of pairs of digit lines. The plurality of pairs of digit lines are coupled to a pair of data bus lines through a plurality of pairs of column selection transfer gates, respectively. Each pair of transfer gates are controlled by a column decode signal generated by a column decoder. The column decoder is generally composed of NOR gate receiving column address signals, a source-follower transistor and a coupling transistor coupled between an output of the NOR gate and a gate of the source follower transistor. The drain of source-follower transistor is supplied with a drive timing signal and the decode signal for controlling the transfer gates is derived from the source of the source-follower transistor. The drive timing signal is generated in response to an externally applied chip enable signal (CE) and takes a boosted level higher than a power voltage V.sub.cc. Therefore, the column selection transfer gates are rendered conductive in the non-saturated, triode region so that signal transfer between the data bus lines and the bit lines is effectively performed.
However, the above drive timing signal is generated by a known boot-strap circuit and the drive timing signal is capacitively boosted above V.sub.cc. Thus, the drive timing signal has a large internal impedance and its boosted level above V.sub.cc gradually falls.
Furthermore, it is common that wiring for carrying the drive timing signal has a plurality of crossing points with other signal wirings such as the data bus lines.
Accordingly, it is difficult to effectively achieve the Read-Modify-Write cycle, in which a read operation is performed on a selected address and immediately thereafter a write operation is made on the same selected address. In this cycle, the drive timing signal is produced during a relatively long period and hence its boosted level inevitably falls below V.sub.cc in the write operation due to leakage of the boosted charge and coupling of the drive timing signal wiring with other wirings. As a result, in the write operation, the level of the drive timing signal is nor more at the boosted level above V.sub.cc but is lower than V.sub.cc and therefore the column selection transfer gates are made conductive in the saturated region and their effective conductances are small. Thus, it is difficult to write new data to the selected address through the transfer gates conductive in the saturated region, resulting in failure in changing data stored in the selected address through the transfer gates.